1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a so-called WCSP (Water Level Chip Size Package) structure.
2. Description of the Related Art
A package having a size equivalent to that of each of semiconductor chips cut out from a semiconductor wafer is generally called “CSP (Chip Size Package)”. CSPs obtained after the semiconductor chips formed on the semiconductor wafer have been sealed with a resin while remaining in a semiconductor wafer state, are called “WCSPs”.
The WCSPs are obtained by effecting a fractionalizing process on a structure containing semiconductor devices formed in plural form on a semiconductor wafer in matrix form according to a wafer process.
There has been known a configuration in which dummy plated layers (dummy columnar electrodes) are formed in areas outside a semiconductor substrate with a view toward making more uniformly the heights of columnar electrodes lying in a semiconductor chip forming area in the above-described WCSP manufacturing process (see the following patent document 1).
There has also been known a configuration wherein solder adhering areas are formed around bump forming patterns on a silicon wafer for the purpose of reducing solder bumps and variations in composition ratio (see the following patent document 2).
Further, there has been known a configuration wherein pressure to be applied is varied at the central part of a substrate and its peripheral portion to carry out compressive sealing with a view toward uniformizing the states of sealing at the central part of the substrate and its peripheral portion upon sealing bumps on the substrate with an encapsulating resin (see the following patent document 3).
An outline of the conventional sealing process will now be explained with reference to FIG. 8. FIG. 8 is a schematic partly plan view showing, in a developed form, a partial area of a semiconductor wafer 100 to describe a conventional protruded electrode sealing process.
The semiconductor wafer 100 includes a semiconductor chip forming area 112 and a peripheral area 114 that surrounds the semiconductor chip forming area 112.
The semiconductor chip forming area 112 is partitioned into matrix form as a plurality of semiconductor chip areas 200 by scribe lines L101.
Protruded electrodes (hereinafter might be called “electrode posts or columnar electrodes”) 118 spaced away from one another in predetermined distances in a 5×5 matrix form are provided within the semiconductor chip area 200.
Here, space or gap areas including the scribe lines L101, among the adjacent semiconductor chip areas 200 are called “scribe streets 140”. Gap areas among adjacent protruded electrodes 118 lying within the same semiconductor chip area 200 are called “protruded electrode-to-protruded electrode areas 142”.
A width w100 of the protrude electrode-to-protruded electrode area 142 in the illustrated example is set to a width different from a width w101 of the scribe street 140. Described specifically, the width w100 of the protruded electrode-to-protruded electrode area 142 is smaller than the width w101 of the scribe street 140. When, for example, the number of the protruded electrodes 118 is fewer, the width w100 of the protruded electrode-to-protruded electrode area 142 might be greater than the width w101 of the scribe street 140.
The illustrated example shows the manner in which an encapsulating resin 134 injected into the central part (the upper left in the figure) of the semiconductor wafer 100 is diffused into and flow to the peripheral area 114. Since the width w100 of the protruded electrode-to-protruded electrode area 142 is different from the width w101 of the scribe street 140 as mentioned above, the flow rate of the encapsulating resin 134 flowing to the wide scribe street 140 and the flow rate of the encapsulating resin 134 flowing to the protruded electrode-to-protruded electrode area 142 are also different from each other. That is, the flow rate of the resin that flows to the scribe street 140 becomes faster than the flow rate of the resin that flows to the protruded electrode-to-protruded electrode area 142.
Patent Document 1    Japanese Laid Open Patent Application No. 2000-332049
Patent Document 2    Japanese Laid Open Patent Application No. 9-139387
Patent Document 3    Japanese Laid Open Patent Application No. 2001-185568
According to the conventional WCSP manufacturing method as described above, the interval between the protruded electrodes formed on the semiconductor wafer, particularly, the interval between the protruded electrodes adjacent to each other with the scribe line interposed therebetween, and the interval between the protruded electrodes adjacent to each other within the semiconductor chip area are different from each other. Therefore, the flow rate of the encapsulating resin becomes non-uniform within the semiconductor chip forming area.
When the flow rate of the encapsulating resin becomes non-uniform within each semiconductor chip area in this way, a void (space) designated at reference numeral 135 can happen in FIG. 8. There is also a fear that a distribution of components of an encapsulating resin like, for example, a filler may be biased due to such a non-uniform flow rate.
Thus, since the semiconductor chip formed in the central part of the semiconductor wafer and each semiconductor chip formed in the vicinity of the peripheral edge of the semiconductor wafer are different in component composition of the encapsulating resin from each other, there is a possibility that variations will occur in the electrical characteristics of each semiconductor device.
For example, the patent documents 1 and 2 do not intend to uniformly form the encapsulating rein within the surface of the wafer although the dummy columnar electrodes and the dummy bumps are formed for the purpose of uniformizing the height of each columnar electrode and the height of each solder bump within the surface of the wafer. Also, the patent document 3 aims to uniformly form the encapsulating resin within the surface of the wafer. However, its realizing means depends on a manufacturing apparatus. Since a die having a complex elevating mechanism is required to realize such a manufacturing apparatus, a capital investment will mount and the manufacturing cost of the semiconductor device will rise consequently. Since such a manufacturing apparatus becomes complicated in operation and adjustment, there is a fear that the quality of each fabricated semiconductor device may vary.